In recent years, a power supply voltage of a semiconductor integrated circuit is becoming lower and lower. One way to achieve a high-speed operation while lowering the power supply voltage is to lower the threshold value of a transistor, however, in this case, the subthreshold leakage in a standby mode cannot be ignored.
As a countermeasure to this, for instance, a configuration shown in FIG. 7 is disclosed in Patent Document 1. In reference to FIG. 7, this configuration comprises fourth stages of CMOS inverters. The first stage CMOS inverter comprises a P-channel MOS transistor PM1 having a source thereof connected to a high-level power supply VDD and an N-channel MOS transistor NM1 having a source thereof connected to a low-level power supply GND and a drain thereof connected in common with the drain of the P-channel MOS transistor PM1 to an output end. The gates of the P-channel MOS transistor PM1 and N-channel MOS transistor NM1 are connected in common to an input terminal IN. The second stage CMOS inverter comprises a P-channel MOS transistor PM2 and a N-channel MOS transistor NM2, with gates of the P-channel MOS transistor PM1 and N-channel MOS transistor NM1 connected in common to the output end of the first stage CMOS inverter. The third stage CMOS inverter comprises a P-channel MOS transistor PM3 and a N-channel MOS transistor NM3, with gates of the P-channel MOS transistor PM3 and N-channel MOS transistor NM13 connected in common to the output end of the second stage CMOS inverter. The fourth stage CMOS inverter comprises a P-channel MOS transistor PM4 and a N-channel MOS transistor NM4, with gates and drains of the P-channel MOS transistor PM4 and N-channel MOS transistor NM4 connected in common to the output end of the third stage CMOS inverter and with an output terminal OUT. The N-channel MOS transistors NM1 and NM3, and the P-channel MOS transistors PM2 and PM4 have low threshold voltages.
In the configuration shown in FIG. 7, on the side that is in an off-state during a standby mode, transistors (PM1, NM2, PM3, and NM4) with threshold values high enough so that subthreshold leakage thereof is acceptable, are used, and on the side that is in an on-state during the standby mode, transistors with low threshold values (NM1, PM2, NM3, and PM4) that meets the demand for high-speed operation are used.
During an operation mode (active mode), the on-state transistors with low threshold values (NM1, PM2, NM3, and PM4) are used to achieve high-speed operation, and by turning off the transistors with high threshold values during the standby mode (the input terminal IN is at a low level), the demand for high-speed operation is met and the subthreshold leakage during the standby mode can be reduced. In other words, during the rising transition when an input signal rises from a low level to a high level, the transistors with low threshold values (NM1, PM2, NM3, and PM4) are turned on and an output signal from the output terminal OUT rises from a low level to a high level promptly.
Meanwhile, as another means for achieving high-speed operation, for instance, a configuration shown in FIG. 8 is disclosed in Patent Document 2. As shown in FIG. 8, this configuration achieves high-speed operation by comprising two paths: a transmission system 1A where the level of an input signal supplied to an input terminal IN changes from a high level to a low level at high speed and a transmission system 2A where the level of the input signal supplied to the input terminal IN changes from a low level to a high level at high speed, and a circuit 6A, to which the output signals from these two transmission systems 1A and 2A are fed, having the function of receiving the output from one of the transmission systems where the signal level changes at high speed and outputting it (CMOS transfer gates TG1 and TG2).
In the circuit shown in FIG. 8, in the transmission system 1A, the driving capability (for instance, W/L ratio—the ratio between the gate width and gate length) of the transistors (PM101 and NM102) that are in an on-state when the input signal supplied to the input terminal IN is at a low level is increased, making the level change of the input signal from a high level to a low level high speed. On the other hand, in the transmission system 2A, the driving capability of the transistors (NM201 and PM202) that are in an on-state when the input signal supplied to the input terminal IN is at a high level is increased, making the level change of the input signal from a low level to a high level high speed.
Furthermore, an output selector unit 5A comprises five stages of inverters 51 to 55 (delay circuit), outputs of the inverter 54 and an the inverter 55 are connected respectively to gates of an N-channel MOS transistor and a P-channel MOS transistor of the CMOS transfer gate TG1, and outputs of the inverter 54 and the inverter 55 are connected respectively to gates of a P-channel MOS transistor and the gate of an N-channel MOS transistor of the CMOS transfer gate TG2. The CMOS transfer gate TG1 is in an on-state when an output signal from an output terminal OUT is at a high level, and the CMOS transfer gate TG2 is in an on-state when the output signal is at a low level. For the rising transition of the input signal from a low level to a high level, a signal (rising transition) is outputted from the output terminal OUT via the on-state transfer gate TG2, and for the falling transition of the input signal from a high level to a low level, a signal (falling transition) is outputted from the output terminal OUT via the on-state transfer gate TG1.
It is configured such that the output signal is delayed by the delay circuit for the input signal that changes from a high level to a low level at high speed, the transfer gate TG2 connected in series to the path of the INH side is turned on when both INL and INH are at a low level, and the transfer gate TG1 connected in series to the path of the INL side is turned on when the both are at a high level. With such a configuration, only the input signal (edge) from the side that changes at high speed can be received and outputted.
Furthermore, for instance, a configuration shown in FIG. 9 is disclosed in Patent Document 3, as a circuit where high-speed operation is made possible by having two input signals and receiving and outputting only the input signal that changes at high speed. In reference to FIG. 9, an open/close control signal generation unit 5B comprises two P-channel MOS transistors PM81 and PM 82 connected in series between a high-level power supply VDD and a low-level power supply GND (ground) and two N-channel MOS transistors NM81 and NM82. Gates of the P-channel MOS transistor PM81 and the N-channel MOS transistor NM81 are connected to an input terminal INF (high-speed falling), and gates of the P-channel MOS transistor PM82 and the N-channel MOS transistor NM82 are connected to an input terminal INR (high-speed rising). Further, this circuit also comprises P-channel MOS transistors PM83 and PM84 having whose sources are connected in common to a high-level power supply VDD, whose gates are connected to a common drain node (M1) of the transistors PM82 and NM82 and to a low-level power supply GND respectively, and whose drains are connected in common, a P-channel MOS transistor PM85 having a source thereof connected to the commonly coupled drains of the P-channel MOS transistors PM83 and PM84, having a gate thereof connected to INF, and having a drain thereof connected to an output terminal OUT, N-channel MOS transistors NM83 and NM84 whose sources are connected in common to a low-level power supply GND, whose gates are connected to the common drain node (M1) of the transistors PM82 and NM82 and to a high-level power supply VDD respectively, and whose drains are connected in common, and an N-channel MOS transistor NM85 having a source thereof connected to the common drain of the N-channel MOS transistors NM83 and NM84, having a gate thereof connected to INR, and having a drain thereof connected to the output terminal OUT.
As described above, the open/close control signal generation unit 5B comprises the inverters (PM81, PM82, NM82, and NM81), which, when the values of two input signals of the input terminals INF and INR are identical, invert the value and output the result to the node M1, and when the values are not identical, place the node M1 in a floating state.
In other words, when the input terminals INF and INR are both at a low level, the P-channel MOS transistors PM81 and PM82 are in an on-state, the N-channel MOS transistors NM81 and NM82 are in an off-state, and the node M1 goes to a power supply potential VDD (high level). At this time, since the N-channel MOS transistor NM83 is turned on, the P-channel MOS transistor PM83 is turned off, the N-channel MOS transistor NM85 is turned off, and the P-channel MOS transistor PM85 is turned on, the output terminal OUT is charged by the power supply VDD via the path of the P-channel MOS transistors PM84 and PM85, and an output signal goes to a high level.
On the other hand, when the input terminals INF and INR are both at a high level, the P-channel MOS transistors PM81 and PM82 are in an off-state, the N-channel MOS transistors NM81 and NM82 are in an on-state, and the node M1 goes to a low-potential power supply voltage GND (low level). At this time, since the P-channel MOS transistor PM83 is turned on, the N-channel MOS transistor NM83 is turned off, the P-channel MOS transistor PM85 is turned off, and the N-channel MOS transistor NM85 is turned on, the output terminal OUT is discharged via the path of the NM85 and NM84 and an output signal goes to a low level.
Furthermore, when the input terminal INF is at a low level and INR is at a high level, the P-channel MOS transistor PM81 is turned on, the P-channel MOS transistor PM82 is turned off, the N-channel MOS transistor NM81 is turned off, the N-channel MOS transistor NM82 is turned on, and the node M1 is in a floating state.
When the input terminal INF is at a high level and INR is at a low level, the N-channel MOS transistor NM81 is turned on, the N-channel MOS transistor NM82 is turned off, the P-channel MOS transistor PM81 is turned off, the P-channel MOS transistor PM82 is turned on, and the node M1 is in a floating state. The output is in a floating state when the values of INF and INR are not identical, and in order to avoid this, high resistance elements using transistors of the same polarity (PM83 and PM84, NM83 and NM84) are connected in parallel for the transistors PM85 and NM85 respectively.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-06-208790 (pp. 2-4, FIG. 1)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-05-7147 (pp. 1-4, FIG. 2)
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2002-135107A (pp. 6-9, FIG. 1)